High performance sparse matrix-vector multiplication on FPGA

High performance sparse matrix-vector multiplication on FPGA

This paper presents the design and implementation of a high performance sparse matrix-vector multiplication (SpMV) on fieldprogrammable gate array (FPGA). By proposing a new storage format to compress the indexes of non-zero elements by exploiting the substructure of the sparse matrix, our SpMV implementation on a reconfigurable computing platform with a multi-channel memory subsystem is capabl...

Sparse Matrix-Vector Multiplication FPGA Implementation

Sparse Matrix-Vector Multiplication using FPGA

On Sparse Matrix-Vector Multiplication with FPGA-Based System

In this paper we report on our experimentation with the use of FPGA-based system to solve the irregular computation problem of evaluating when the matrix A is sparse. The main features of our matrix-vector multiplication algorithm are (i) an organization of the operations to suit the FPGA-based system ability in processing a stream of data, and (ii) the use of distributed arithmetic technique t...

Performance aspects of sparse matrix-vector multiplication

Sparse matrix-vector multiplication (shortly SpM×V) is an important building block in algorithms solving sparse systems of linear equations, e.g., FEM. Due to matrix sparsity, the memory access patterns are irregular and utilization of the cache can suffer from low spatial or temporal locality. Approaches to improve the performance of SpM×V are based on matrix reordering and register blocking [...